FIG. 1 (Prior Art) is a simplified cross-sectional diagram of an NPN bipolar transistor 1. When transistor 1 is conducting current, current flows from collector electrode 2, through N+ type sinker region 3, through N+ type buried layer 4, through N- type collector region 5, through P type base region 6, through N+ type emitter region 7, and to emitter electrode 8. The arrow labeled e points in the opposite direction because electron flow is defined to be opposite of current flow. N+ type buried layer 4 and N+ type sinker region 3 form a low resistance connection from the bottom surface of N- type collector region 5 to collector electrode 2. A base current flows from base electrode 9, through low impedance N+ type base contact region 10, through P type base region 6, through N+ type emitter region 7, and to emitter electrode 8. The arrow labeled + indicates that current conduction in the base region is primarily due to the movement of holes. The transistor structure is formed on a P type substrate 11. Field oxide 12 is formed around the active area which contains the emitter and base regions.
A bipolar transistor generally should have a thin base region so that its .beta. (.beta.=I.sub.C /I.sub.B) will be high. In the structure of transistor 1, however, the thickness of the base region 6 underneath the emitter region 7 should not be made significantly thinner than the thickness of the emitter region 7 because the magnitude of the variations in the thickness of the implanted and diffused emitter region 7 increases as the thickness of the emitter region 7 increases. An emitter region which is much thicker than the underlying base region may therefore have variations which are of significant magnitude when compared to the thickness of the thin base region. Consistent base thicknesses in all the bipolar transistors on a die may therefore be difficult to achieve.
FIG. 2 (Prior Art) is a simplified cross-sectional diagram of another type of NPN bipolar transistor 13 called a "poly-emitter" transistor. The poly-emitter type bipolar transistor is generally suited for fabrication on the same die with field effect transistors in a BiCMOS process. To form bipolar transistor 13, a buried N+ type layer 14 is formed in a P- type substrate 15 by ion implanting N type dopants and a subsequent anneal to repair damage to the crystal structure caused by the implant. An N- type epitaxial silicon layer is then grown over the N+ type buried layer to form upper surface 16. Using different masks and different dopants, N wells are formed for P channel field effect transistors on the die and P wells are formed for the N channel field effect transistors on the die. When the N wells are being formed, N type dopants also dope the portion of the epitaxial silicon which will ultimately form an N- type collector region 17 of the bipolar transistor 13. Field oxide 18 is then grown around the active area of the bipolar transistor using a LOCOS process. An N+ type implant is performed to form an N+ type sinker (not shown) for connecting a collector electrode (not shown) to the N+ type buried layer 14.
A gate oxide for the field effect transistors is then formed over the epitaxial silicon surface 16 and a mask is used to selective etch away the portion of this gate oxide which is in the active area of bipolar transistor 13. P type dopants are then selectively implanted in the bipolar transistor active area thereby doping the epitaxial silicon which will form an intrinsic base region 19.
A layer 20 (see FIGS. 3A and 3B) of polysilicon is then deposited and doped and a layer 21 of silicide is optionally formed over the polysilicon. Not only will this doped polysilicon be fashioned to form the gates of the field effect transistors, but this doped polysilicon will also serve to supply dopants for forming the emitter region 22 of bipolar transistor 13.
FIGS. 3A and 3B (Prior Art) illustrate a photoresist mask 23 used for forming the gates of the field effect transistors and for forming the polysilicon emitter feature 28 of bipolar transistor 13. Note that thin gate oxide 24 is present in the field effect transistor structure but not in the bipolar transistor structure. The silicide layer 21, the polysilicon layer 20 and the gate oxide layer 24 is then etched.
FIGS. 4A and 4B (Prior Art) illustrate structures which result after etching. An overetch is performed to make sure that all polysilicon is removed. Because there is no gate oxide in the bipolar structure, etching proceeds past silicon surface 16 thereby forming a trench as illustrated in FIG. 4A. There is no such trench in the field effect transistor structure, however, because the gate oxide 24 slows the etching as illustrated in FIG. 4B.
In a lightly doped drain (LDD) field effect transistor process, the P channel field effect transistor active areas and the bipolar active areas receive a light P- type blanket implant and the N channel field effect transistor active areas receive a light N- type blanket implant. An oxide is then formed over the entire wafer and the oxide is etched so that oxide spacers 25 are formed at the edges of the gates and at the edges of the polysilicon emitter feature 28 of the bipolar transistor 13.
With relatively lightly doped regions 26 underneath the spacers 25, the P channel field effect transistor active areas and the bipolar active areas receive a more heavy P+ type blanket implant and the N channel field effect transistor active areas receive a more heavy N+ type blanket implant. Accordingly, heavily doped extrinsic base regions 27 are formed outside the lightly doped regions 26 in the bipolar transistor active area.
The bipolar transistor of FIG. 2 generally has an increased .beta. when compared with the .beta. of the structure of FIG. 1. One possible explanation is that the polysilicon emitter feature 28 to emitter region 22 boundary impedes the movement of holes. Because the base current is a current which flows from P+ type extrinsic base region 27, through lightly doped P- type link region 26, through intrinsic base region 19, through N+ type emitter region 22 and through N+ type polysilicon emitter feature 28 to an emitter electrode (not shown), impeding the movement of holes at the polysilicon boundary reduces the base current I.sub.B. Because .beta. is the collector current I.sub.C divided by the base current I.sub.B, the .beta. of the transistor is increased.
FIG. 5 (Prior Art) is a top down view showing the boundary 29 of the base implant mask used to remove gate oxide from the bipolar transistor active area and used to implant P type dopants into intrinsic base region 19. Solid line 30 illustrates the boundary of the actual active area. Solid line 31 illustrates the top down outline of the polysilicon emitter feature 28. FIG. 2 is a cross-sectional diagram taken along line BB of FIG. 5 whereas FIG. 6 is a cross-sectional diagram taken along line CC of FIG. 5. As shown in FIG. 6 (Prior Art), oxide spacers 25 in FIG. 2 and oxide spacers 25 in FIG. 6 are actually different cross-sectional views of the same single spacer which surrounds the periphery of the polysilicon emitter feature 28.
Not only is it generally desirable to have a high .beta., but it also generally desirable for the transistor to have a high cutoff frequency f.sub.T. Decreasing the resistance r.sub.c in the collector current path between the intrinsic base region 19 and the buried layer 14 increases the cutoff frequency f.sub.T of the transistor. It therefore would be desirable to bring the bottom of P type intrinsic base region 19 closer to the top of buried layer 14 so that electrons would pass through less relatively resistive N- type collector region silicon on their path to buried layer 14. Doing so, however, may result in a transistor which has an undesirably low base-to-collector breakdown voltage (BV.sub.cbo). The lowest extent of the extrinsic base region 27 determines the minimum distance D1 between the bottom of the transistor base and the top of the buried layer 14. This minimum distance determines the base-to-collector voltage at which the transistor will breakdown. The depth of extrinsic base region 27 therefore generally limits how close the bottom of P type base region 19 can be brought to the top of buried layer 14 for a required base-to-collector breakdown voltage.
A bipolar transistor structure is therefore sought which can be manufactured on the same die as field effect transistors, which has an adequately high .beta., which has an adequately high cutoff frequency f.sub.T, and which has an adequately high base-to-collector breakdown voltage.